1. Field of the Invention
Embodiments of the present invention relate generally to image sensors, pixels, and methods and, in specific embodiments, to image sensors with global shutter pixels.
2. Related Art
Image sensors have found wide application in consumer and industrial electronics, and have enabled an explosion in a number of digital cameras and digital video devices used for work and entertainment.
FIG. 1 illustrates an architecture of a related art image sensor 1. The image sensor 1 includes a pixel array 2, a row driver 4, column readout circuitry 7, and a column circuit timing controller 9. The pixel array 2 includes pixels 3 that are arranged in rows and columns. Each pixel 3 includes a light sensitive element, such as a photodiode, or the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel 3 is configured to produce an analog pixel signal based on the sampled light intensity. The row driver 4 supplies control signals to the pixels 3 in the pixel array 2 to control an operation of the pixels 3.
Pixels 3 that are in a same row of the pixel array 2 share common row control signals from the row driver 4. For example, pixels 3 in a first row of the pixel array 2 share common row control lines 51 for receiving control signals from the row driver 4. Similarly, pixels 3 in a second row of the pixel array 2 share common row control lines 52 for receiving control signals from the row driver 4, and pixels 3 in an nth row of the pixel array 2 share common row control lines 5n for receiving control signals from the row driver 4. Pixels 3 that are in a same column of the pixel array 2 share a common column readout line to provide output. For example, pixels 3 in a first column of the pixel array 2 share a column readout line 61, pixels 3 in a second column of the pixel array 2 share a column readout line 62, and pixels 3 in an mth column of the pixel array 2 share a column readout line 6m. The row driver 4 controls the pixels 3 to provide output row by row.
FIG. 2 illustrates an example of a conventional pixel 3. The pixel 3 illustrated in FIG. 2 is provided as an example of a pixel in a kth column of a pixel array, such as the pixel array 2 (refer to FIG. 1). The pixel 3 includes a substrate 20, a photodiode (PD) 21, a transfer gate 22, a storage diffusion 23, an anti-blooming gate 24, an anti-blooming gate diffusion 25, a reset transistor 26, a source follower transistor (SF) 27, and a row select transistor 28. The storage diffusion 23 may also be called a floating diffusion (FD) node 23 or a readout node 23. The anti-blooming gate 24 may also be called a shutter gate 24. The photodiode 21 may be, for example, a pinned photodiode that collects charge during exposure based on the light intensity of a corresponding portion of a scene being imaged.
The transfer gate 22 is connected to receive a transfer control signal (TX), and the transfer gate 22 is controllable by the transfer control signal TX to transfer charge from the photodiode 21 to the storage diffusion 23. The anti-blooming gate 24 is connected to receive an anti-blooming control signal (AB), and the anti-blooming gate 24 is controllable by the anti-blooming control signal AB to allow for charge to be drained from the photodiode 21 to the anti-blooming gate diffusion 25. The anti-blooming gate diffusion 25 is connected to a reset voltage source (not shown) that supplies a reset voltage (Vrst).
A first terminal of the reset transistor 26 is connected to the reset voltage source that provides the reset voltage (Vrst). A gate of the reset transistor 26 is connected to receive a reset control signal (RST). A second terminal of the reset transistor 26 is connected to the storage diffusion 23 and to a gate of the source follower transistor 27. The gate of the source follower transistor 27 is connected to the storage diffusion 23 and to the second terminal of the reset transistor 26. A first terminal of the source follower transistor 27 is connected to a voltage source (not shown) that supplies a voltage (Vdd).
A second terminal of the source follower transistor 27 is connected to a first terminal of the row select transistor 28. A gate of the row select transistor 28 is connected to receive a row select control signal (ROW). A second terminal of the row select transistor 28 is connected to a column readout line 6k for providing a pixel output signal (pout) for the pixel 3 on the column readout line 6k. Thus, the pixel 3 is controlled with the four control signals AB, TX, RST, and ROW, and the pixel 3 provides an output signal (pout).
If space allows, the anti-blooming gate diffusion 25 and a source terminal of the reset transistor 26 receive power from the reset voltage source (not shown) supplying the reset voltage Vrst, which can be run either horizontally, or vertically, or as a mesh in a pixel array. The source follower transistor 27 is powered from the voltage source (not shown) supplying Vdd, which is run as a vertical wire in each column of a pixel array. If space is tight, Vrst can be combined with Vdd.
FIG. 3 illustrates a circuit diagram representation of the pixel 3 of FIG. 2. In FIG. 3, the transfer gate 22 and the anti-blooming gate 24 are represented as gates of transistors, with a first terminal of each of those transistors connected to the photodiode 21. Those two transistors plus the reset transistor 26, the source follower transistor 27, and the row select transistor 28 equal five transistors, so the pixel 3 is conventionally referred to as a five transistor (5T) pixel. The floating diffusion node 23 is connected to the gate of the source follower transistor 27. The anti-blooming gate diffusion 25 is connected to a voltage source (not shown). The pixel 3 is connected to provide output on the column readout line 6k.
An operation of the pixel 3 is now described with reference to FIGS. 2 and 3. When the anti-blooming control signal AB applied to the anti-blooming gate 24 is HIGH, all charges from the photodiode 21 are drained out into Vrst or Vdd (whatever is connected to the anti-blooming gate diffusion 25). When an image capture operation is initiated for the pixel 3, the anti-blooming control signal AB and the transfer control signal TX are controlled to be LOW, so that charge is collected during exposure in the photodiode 21. Prior to transferring the charge, the floating diffusion node 23 is cleared either with a reset pulse by controlling the reset control signal RST to be HIGH and then LOW, or the floating diffusion node 23 remained empty from a previous readout from the floating diffusion node 23.
The transfer of charge from the photodiode 21 to the floating diffusion node 23 is then performed by controlling the transfer control signal TX applied to the transfer gate 22 to be HIGH. After the transfer is done, the transfer control signal TX is controlled to be LOW, and a new exposure in the photodiode 21 can start, controlled by the anti-blooming control signal AB. The anti-blooming control signal AB can be controlled to be HIGH to cause charge to be drained from the photodiode 21, and then exposure starts with bringing the anti-blooming control signal AB to LOW. The readout of charge from the pixel 3 is done in parallel with an exposure that collects charge for a subsequent readout.
The readout from the pixel 3 can start right after the transfer of the charge from the photodiode 21 to the floating diffusion node 23. The readout is performed row by row in the pixel array 2 (refer to FIG. 1). To perform the readout from the pixel 3, the row select control signal ROW is controlled to be HIGH, and a pixel signal corresponding to a charge at the floating diffusion node 23 is read out over the column readout line 6k. The row select control signal ROW is then controlled to be LOW, and the reset control signal RST is controlled to be HIGH to empty the floating diffusion node 23. The reset control signal RST is then controlled to be LOW and the row select control signal ROW is controlled to be HIGH to read out a potential (the reset value) of the empty floating diffusion node 23 over the column readout line 6k.
The pixel signal corresponding to the charge at the floating diffusion node 23 prior to reset and the reset value corresponding to the reset potential at the floating diffusion node 23 after reset are provided to a corresponding column readout circuit 8 (refer to FIG. 1) for the column in which the pixel 3 is located. The column readout circuit 8 digitizes a difference between the pixel signal and the signal of the reset potential to provide a digital output representing the charge collected by the pixel 3 during the corresponding exposure.
With reference again to FIG. 1, the column readout circuitry 7 includes a column readout circuit 8 for each column of pixels 3 in the pixel array 2. Each column readout circuit 8 is connected to receive analog signals from a corresponding column readout line, and is configured to provide digital output on a corresponding output line. For example, the column readout circuit 8 for the first column is connected to the column readout line 61 for receiving input, and is connected to an output line 111 for providing output. Similarly, the column readout circuit 8 for the second column is connected to the column readout line 62 for receiving input, and is connected to an output line 112 for providing output, and the column readout circuit 8 for the mth column is connected to the column readout line 6m for receiving input, and is connected to an output line 11m for providing output. The column circuit timing controller 9 is configured to provide control signals to the plurality of column readout circuits 8 over one or more control lines 10.
There are various types of shutter operations. One example type of shutter operation is a global shutter operation. Pixels that can be used for global shutter operations are called global shutter pixels. An example of a global shutter pixel is the 5T pixel illustrated in FIG. 3. In a global shutter operation, the transfer of charge from the photodiode of each pixel to the pixel storage of each pixel is done simultaneously for all pixels in the pixel array, so the exposure ends at a same time for all the pixels. The beginning of the exposure in the global shutter operation can be controlled, for example, by using a shutter or anti-blooming gate.
The 5T global shutter pixel is extensively used in high speed imaging. The 5T pixel allows for simultaneous acquisition of an image in all pixels of an image sensor and it allows for exposure control independent of the readout. As explained above, the photodiode in a 5T pixel is controlled with two gates. One of the gates is the transfer gate to transfer and store the useful signal charge, and the other gate is the shutter gate or anti-blooming gate which serves for exposure control and for spilling an excessive photodiode charge (antiblooming protection). In a preferred case of the photodiode being a pinned photodiode, either of the gates is able to completely empty the photodiode. FIG. 4 illustrates a typical topology of the placement of the transfer (TX) gate and the anti-blooming (AB) gate with respect to the photodiode (PD).
The 5T pixel has a number of known performance issues, such as issues related to large pixel size and to very high speed imaging. When the frame rate goes up, and the exposure becomes shorter and shorter (e.g. there are applications requiring 1 million frames per second with a frame read time of 1 μs), less and less photons strike the pixel for the exposure time. One natural solution to very high speed imaging is to use a larger pixel which can collect more photons from the light of the same intensity.
However, there is a collection time limitation inherent to the detector itself. For an ideal case of a flat pinned photodiode, the charge in the channel of the pinned diode is cleared through a diffusion process. If the typical size of the photodiode is L (say, this is the longest path in the pixel for carriers to travel to the respective TX or AB gate, then the typical travel time constant is L2/D, where D is the diffusion coefficient.
For a typical pixel size of 10 μm, and a diffusion coefficient of 10 cm2/s, the characteristic transfer time in the channel of the photodiode is 10−7 s, which is 100 ns. It takes up to 5 time constants to fully transfer the charge. Also, the potential in the pinned photodiode channel may have a “bowl” shape slowing down the transfer. Thus, the response time of the conventional pinned photodiode of a 10 μm size is limited to approximately within a range of 500 ns to 1 μs. If the photodiode size grows to 20 μm to 30 μm to address the photon limitation issue, the pixel transfer time slows down by another factor of 4 to 9, which means the topology of the photodiode and the gates in FIG. 4 cannot be used for lag-less operation of the 20 μm to 30 μm size pixels operating with exposure time of 1 μs.
Similar problems exist with pinned photodiode pixels used for phase detection. In a lock in photodiode detector of a 10 μm size with a flat potential pinned channel, and which has 2 gates, a period of efficient de-modulation of light is limited to 500 ns, so the efficiency of modulation starts falling down at a frequency of 1 MHz and above.
A pinned photodiode pixel is described by Berezin et al. in U.S. Pat. No. 6,750,485, entitled “Lock-In Pinned Photodiode Photodetector,” issued Jun. 15, 2004, the entire contents of which are incorporated by reference herein, and which is herein referred to as “Berezin.” Berezin describes a pinned photodiode pixel with 4 transfer gates. A high frequency 4-phase clock goes around and sends photocharge from the photodiode into 4 respective outputs for accumulation. This process is repeated 100-1000 or more times, but each output storage keeps the phase of the charges collected during the respective phase. With two outputs, one output collects signal chopped during [0°-180°] then [360°-540°], while the other output collects the signals coming to the pixel during phases [180°-360°], [540°-720°], and so on.
That is the principle of in-pixel phase detection. It allows to use modulated light (˜10-100 MHz) and measure a distance from the sensor to an object based on Time-of-Flight (TOF). A similar pixel to the pixel described in Brezin is described by Kawahito in U.S. Pat. No. 7,436,496, entitled “Distance Image Sensor,” issued Oct. 14, 2008, the entire contents of which are incorporated by reference herein, and which is herein referred to as “Kawahito.”
Another problem with very high speed imaging is that a ratio of the transfer time to the total frame time becomes too large. In the example of a 10 μm pixel above, one needs to allocate at least 500 ns to the transfer through TX gate to avoid image lag. This means that, if the sensor operates at 1 million frames/s, 500 ns is spent for the transfer, and there is only 500 ns left to read out the frame of the shuttered image. FIG. 5 illustrates a frame timing of a conventional 5T pixel. The readout from the pixel array cannot be done during the transfer time, which is Vertical Blank (VB). The TX transfer time takes a noticeable portion of the entire frame time, so that less time is left for pixel readout.